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ADR-110: ESP32-C6 firmware extension (#764)
Closes the firmware-side ADR-110 design at v0.7.0-esp32 after a 38-iter /loop SOTA sprint. Headline (bench, COM9+COM12 ESP32-C6): - 99.56% cross-board RX, 104.1 µs smoothed offset stdev (≤100 µs §2.4 target met) - 3.95× EMA suppression, 1.4 ppm crystal skew preserved 4 firmware releases: v0.6.7 / v0.6.8 / v0.6.9 / v0.7.0-esp32. 42 ADR-110 unit tests, 1761 v2 workspace tests, full Firmware CI + QEMU green.
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rUv
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/**
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* @file c6_lp_core.c
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* @brief LP-core wake-on-motion hibernation — ADR-110 Phase 5 (full).
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*
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* Two operating modes, controlled by CONFIG_C6_LP_CORE_ENABLE:
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*
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* 1. ENABLED — real LP-core RISC-V program polls the wake GPIO at
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* LP_TIMER cadence (default 10 ms), debounces N matching samples,
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* and triggers an HP wake via `ulp_lp_core_wakeup_main_processor()`.
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* HP enters deep sleep with `ESP_SLEEP_WAKEUP_ULP` as the source.
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* Targets ~5 µA average current (datasheet figure for LP-core +
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* RTC peripherals powered down). The LP binary is built by
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* `ulp_embed_binary(...)` in main/CMakeLists.txt from lp_core/main.c.
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*
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* 2. DISABLED — falls back to plain deep-sleep + GPIO wake-up
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* (`esp_deep_sleep_enable_gpio_wakeup`). No debounce, no
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* sub-10 µA floor, but no LP toolchain dependency either.
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* This is the path the v0.6.6 firmware shipped with.
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*
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* Both paths share `c6_lp_core_arm()` / `c6_lp_core_hibernate_and_wait()`
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* so call sites in main.c don't change between modes.
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*/
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#include "sdkconfig.h"
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#if defined(CONFIG_IDF_TARGET_ESP32C6) && defined(CONFIG_ULP_COPROC_TYPE_LP_CORE)
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#include "c6_lp_core.h"
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#include "esp_log.h"
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#include "esp_sleep.h"
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#include "driver/rtc_io.h"
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#include "soc/soc_caps.h"
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#include <string.h>
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#if defined(CONFIG_C6_LP_CORE_ENABLE)
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#include "ulp_lp_core.h"
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/* ulp_main.h is auto-generated by `ulp_embed_binary(ulp_main, ...)` and
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* exports every `volatile` global from lp_core/main.c with the `ulp_`
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* prefix. Include is guarded so disabled builds don't try to find a
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* file the build system hasn't generated. */
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#include "ulp_main.h"
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extern const uint8_t ulp_main_bin_start[] asm("_binary_ulp_main_bin_start");
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extern const uint8_t ulp_main_bin_end[] asm("_binary_ulp_main_bin_end");
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#endif
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static const char *TAG = "c6_lp";
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static int s_wake_gpio = -1;
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static bool s_active_high = true;
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static bool s_armed = false;
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#ifndef CONFIG_C6_LP_POLL_PERIOD_US
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#define CONFIG_C6_LP_POLL_PERIOD_US 10000 /* 100 Hz default poll cadence */
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#endif
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#ifndef CONFIG_C6_LP_DEBOUNCE_SAMPLES
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#define CONFIG_C6_LP_DEBOUNCE_SAMPLES 3
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#endif
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esp_err_t c6_lp_core_arm(int wake_gpio, bool active_high)
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{
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if (wake_gpio < 0) {
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ESP_LOGE(TAG, "invalid wake_gpio=%d", wake_gpio);
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return ESP_ERR_INVALID_ARG;
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}
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s_wake_gpio = wake_gpio;
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s_active_high = active_high;
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/* GPIO must be in the LP/RTC domain for either wake path. */
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esp_err_t ret = rtc_gpio_init(wake_gpio);
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if (ret != ESP_OK) {
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ESP_LOGE(TAG, "rtc_gpio_init(%d) failed: %s", wake_gpio, esp_err_to_name(ret));
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return ret;
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}
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rtc_gpio_set_direction(wake_gpio, RTC_GPIO_MODE_INPUT_ONLY);
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/* Floating inputs in deep sleep are an antenna — disable internal pulls
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* only if the user has an external pull on the motion line; we leave
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* default pulls so a disconnected pin doesn't toggle randomly. */
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#if defined(CONFIG_C6_LP_CORE_ENABLE)
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/* --- Real LP-core path --- */
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/* On C6, LP-IO maps 1:1 to GPIO for indices 0..7. Validate. */
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if (wake_gpio > 7) {
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ESP_LOGE(TAG, "LP-core path requires LP-IO 0..7, got GPIO %d", wake_gpio);
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return ESP_ERR_INVALID_ARG;
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}
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/* Load the LP-core binary blob. */
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esp_err_t err = ulp_lp_core_load_binary(
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ulp_main_bin_start,
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(size_t)(ulp_main_bin_end - ulp_main_bin_start));
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "ulp_lp_core_load_binary failed: %s", esp_err_to_name(err));
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return err;
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}
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/* Hand the GPIO parameters to the LP program via shared symbols.
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* These are declared `volatile` in lp_core/main.c so the HP write
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* is observed by LP on the next iteration. */
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ulp_wake_gpio_num = (uint32_t)wake_gpio;
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ulp_wake_active_high = active_high ? 1u : 0u;
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ulp_debounce_samples = CONFIG_C6_LP_DEBOUNCE_SAMPLES;
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ulp_motion_count = 0;
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ulp_poll_count = 0;
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ulp_last_gpio_level = 0;
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/* Configure LP-timer wakeup at the configured poll period and start the
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* LP-core. `ulp_lp_core_run` is non-blocking; the LP core begins running
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* the program immediately and the HP core can proceed to deep sleep. */
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ulp_lp_core_cfg_t cfg = {
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.wakeup_source = ULP_LP_CORE_WAKEUP_SOURCE_LP_TIMER,
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.lp_timer_sleep_duration_us = CONFIG_C6_LP_POLL_PERIOD_US,
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};
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err = ulp_lp_core_run(&cfg);
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "ulp_lp_core_run failed: %s", esp_err_to_name(err));
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return err;
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}
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/* Tell deep-sleep that the LP-core is our wake source. */
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err = esp_sleep_enable_ulp_wakeup();
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "esp_sleep_enable_ulp_wakeup failed: %s", esp_err_to_name(err));
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return err;
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}
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s_armed = true;
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ESP_LOGI(TAG, "LP-core armed: gpio=%d active_%s debounce=%d poll=%d µs",
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wake_gpio, active_high ? "high" : "low",
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CONFIG_C6_LP_DEBOUNCE_SAMPLES, CONFIG_C6_LP_POLL_PERIOD_US);
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return ESP_OK;
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#else
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/* --- Fallback path: plain deep-sleep GPIO wakeup (~10 µA floor) --- */
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uint64_t mask = 1ULL << wake_gpio;
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esp_deepsleep_gpio_wake_up_mode_t mode = active_high
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? ESP_GPIO_WAKEUP_GPIO_HIGH
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: ESP_GPIO_WAKEUP_GPIO_LOW;
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esp_err_t err = esp_deep_sleep_enable_gpio_wakeup(mask, mode);
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "enable_gpio_wakeup failed: %s", esp_err_to_name(err));
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return err;
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}
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s_armed = true;
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ESP_LOGI(TAG, "GPIO-wakeup armed (no LP-core): gpio=%d active_%s",
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wake_gpio, active_high ? "high" : "low");
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return ESP_OK;
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#endif
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}
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void c6_lp_core_hibernate_and_wait(void)
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{
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if (!s_armed) {
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ESP_LOGW(TAG, "hibernate called without arm — sleeping with no wake source");
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}
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/* Power down the RTC peripheral domain — the LP-core itself stays
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* powered on the LP power domain so it can keep polling. */
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esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_OFF);
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#if defined(CONFIG_C6_LP_CORE_ENABLE)
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ESP_LOGI(TAG, "entering deep sleep — LP-core polling, target ≤5 µA");
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#else
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ESP_LOGI(TAG, "entering deep sleep — GPIO wakeup, target ~10 µA");
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#endif
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esp_deep_sleep_start();
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/* Never returns. */
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}
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bool c6_lp_core_was_motion_wake(void)
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{
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esp_sleep_wakeup_cause_t cause = esp_sleep_get_wakeup_cause();
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#if defined(CONFIG_C6_LP_CORE_ENABLE)
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/* Real LP-core path: wakeup cause is ULP (LP-core triggered HP). */
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if (cause == ESP_SLEEP_WAKEUP_ULP) return true;
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#endif
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/* Fallback path or alternate GPIO wakeup. */
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return cause == ESP_SLEEP_WAKEUP_GPIO || cause == ESP_SLEEP_WAKEUP_EXT1;
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}
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#if defined(CONFIG_C6_LP_CORE_ENABLE)
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uint32_t c6_lp_core_motion_count(void)
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{
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return (uint32_t)ulp_motion_count;
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}
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uint32_t c6_lp_core_poll_count(void)
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{
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return (uint32_t)ulp_poll_count;
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}
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#else
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uint32_t c6_lp_core_motion_count(void) { return 0; }
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uint32_t c6_lp_core_poll_count(void) { return 0; }
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#endif
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#endif /* CONFIG_IDF_TARGET_ESP32C6 && CONFIG_ULP_COPROC_TYPE_LP_CORE */
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