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feat: ADR-039 edge intelligence — on-device CSI processing pipeline

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Implements a dual-core edge processing system for ESP32-S3:
- Lock-free SPSC ring buffer (Core 0 produces, Core 1 consumes)
- Tier 1: phase unwrap, Welford stats, top-K subcarrier selection, delta compression
- Tier 2: presence/motion detection, vital signs (breathing/heart rate via biquad IIR), fall detection
- Vitals UDP packet (magic 0xC5110002, 32 bytes, sent at 1 Hz)
- NVS/Kconfig configurable (edge_tier, thresholds, intervals)
- Backward compatible: tier=0 (default) is a no-op
- GitHub Actions firmware CI: build, binary size gate, credential scan, flash image verification
- Binary: 777 KB (24% free in 1 MB partition)

Co-Authored-By: claude-flow <ruv@ruv.net>
This commit is contained in:
ruv
2026-03-02 19:55:35 -05:00
parent 14902e6b4e
commit e9bb4faf53
9 changed files with 1671 additions and 5 deletions
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firmware/esp32-csi-node/main/CMakeLists.txt
+1 -1
View File
@@ -1,4 +1,4 @@
idf_component_register(
SRCS "main.c" "csi_collector.c" "stream_sender.c" "nvs_config.c"
SRCS "main.c" "csi_collector.c" "stream_sender.c" "nvs_config.c" "edge_processing.c"
INCLUDE_DIRS "."
)