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rUv
00a234eda8
Closes the firmware-side ADR-110 design at v0.7.0-esp32 after a 38-iter /loop SOTA sprint. Headline (bench, COM9+COM12 ESP32-C6): - 99.56% cross-board RX, 104.1 µs smoothed offset stdev (≤100 µs §2.4 target met) - 3.95× EMA suppression, 1.4 ppm crystal skew preserved 4 firmware releases: v0.6.7 / v0.6.8 / v0.6.9 / v0.7.0-esp32. 42 ADR-110 unit tests, 1761 v2 workspace tests, full Firmware CI + QEMU green.
29 lines
1.1 KiB
Plaintext
29 lines
1.1 KiB
Plaintext
# ADR-110 apples-to-apples S3 overlay for fair vs-C6 size comparison.
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# Same target as production S3 but with the features that aren't on C6 disabled:
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# - No AMOLED display (ADR-045 — C6 has no PSRAM for framebuffers)
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# - No WASM3 (ADR-040 — same reason)
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# - No mmWave fusion (separate board)
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# This is NOT a production build — only used to answer "is C6 smaller than S3
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# once you strip the S3-only features?"
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#
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# Build:
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# cp sdkconfig.defaults.s3-fair sdkconfig.defaults && idf.py set-target esp32s3 && idf.py build
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# # Restore default: git checkout sdkconfig.defaults
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CONFIG_IDF_TARGET="esp32s3"
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CONFIG_PARTITION_TABLE_CUSTOM=y
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CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions_4mb.csv"
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CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
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CONFIG_ESPTOOLPY_FLASHSIZE="4MB"
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CONFIG_COMPILER_OPTIMIZATION_SIZE=y
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CONFIG_ESP_WIFI_CSI_ENABLED=y
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CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y
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CONFIG_LOG_DEFAULT_LEVEL_INFO=y
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CONFIG_LWIP_SO_RCVBUF=y
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CONFIG_ESP_MAIN_TASK_STACK_SIZE=8192
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CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=8192
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# Disable display + WASM + mmWave for apples-to-apples vs C6.
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# CONFIG_DISPLAY_ENABLE is not set
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# CONFIG_WASM_ENABLE is not set
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