mirror of
https://github.com/ruvnet/RuView
synced 2026-07-20 17:03:24 +00:00
ruv
f23e34ee5c
`firmware/esp32-csi-node` now builds for both `esp32s3` (existing
production) and `esp32c6` (new research / battery-seed target) from
the same source tree. ESP-IDF auto-applies `sdkconfig.defaults.esp32c6`
when the target is set to esp32c6; every C6 module is gated on
CONFIG_IDF_TARGET_ESP32C6 (or the SOC_WIFI_HE_SUPPORT capability) so
the S3 build path is byte-identical to today.
New modules (all #ifdef-gated, no-op stubs on S3):
- c6_twt.{h,c} — iTWT wrapper, graceful AP-NACK fallback
- c6_timesync.{h,c} — 802.15.4 beacon-based mesh time-sync, EUI-64
leader election, c6_timesync_get_epoch_us()
- c6_lp_core.{h,c} — wake-on-motion deep-sleep helper (ext1 path
this cut; real LP-core polling deferred)
ADR-018 frame extension:
- byte 18: PPDU type (0=HT/legacy, 1=HE-SU, 2=HE-MU, 3=HE-TB)
- byte 19: bandwidth + STBC + 802.15.4-sync-valid flags
- Magic 0xC5110001 unchanged — backwards compatible
- Dual-branch encoding handles both struct variants of
wifi_pkt_rx_ctrl_t (legacy S3 / HE C6) per CONFIG_SOC_WIFI_HE_SUPPORT
Critical bug fixed during live witness collection (verified across 3
boards on COM6/COM9/COM12):
- c6_timesync.c read MAC into a 6-byte buffer and ran MAC-48->EUI-64
conversion. But esp_read_mac(ESP_MAC_IEEE802154) returns 8 bytes
already in EUI-64 form on C6 — code was double-inserting FFFE.
Boot log was 206ef1fffefffe17, fix yields 206ef1fffe17278c which
matches esptool's eFuse reading exactly.
Tooling:
- CI workflow (firmware-ci.yml) extended with c6-4mb matrix row +
ADR-110 host-unit-test step
- Host unit tests for pure functions (mac48_to_eui64,
eui64_bytes_to_u64, PPDU encoding both branches) — runs on Ubuntu CI
- Multi-board live-capture harness (test/capture-3board-experiment.py)
- Witness bundle script records SHA-256s for s3-adr110, c6-adr110, and
s3-fair-adr110 (apples-to-apples) binary archives
Honest empirical findings (full report in docs/WITNESS-LOG-110.md):
- Verified live on 3 C6 boards: boot, 802.15.4 init w/ correct EUIs,
WiFi STA reaching assoc->run on ruv.net, TWT setup attempted +
gracefully NACKed (AP is 11n-only, TWT Responder:0), HE-MAC firmware
loaded
- NOT verified (need 11ax AP / second-channel exp / INA meter):
HE-LTF subcarrier expansion, TWT cadence determinism, ±100 µs sync
alignment, 5 µA hibernation
- Bug found: leader election doesn't step down under live WiFi load —
likely 2.4 GHz radio coex preemption (WiFi ch 5 vs 15.4 ch 15);
follow-up task #30
- Apples-to-apples size: S3-no-display = 886 KB, C6 = 1003 KB
(C6 is 13% LARGER for equivalent CSI features; the extra is the
802.15.4 + OpenThread stack that S3 lacks)
Tracking: ruvnet/RuView#762
Co-Authored-By: claude-flow <ruv@ruv.net>
87 lines
2.9 KiB
C
87 lines
2.9 KiB
C
/**
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* @file c6_lp_core.c
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* @brief LP-core wake-on-motion hibernation — ADR-110 Phase 5 skeleton.
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*
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* The actual LP-core binary lives in a separate component subproject
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* compiled with the LP RISC-V toolchain (`riscv32-esp-elf` with LP-core
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* memory layout). For the P5 skeleton we ship just the HP-side arming
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* + deep-sleep entry, using esp_sleep_enable_ext1_wakeup() as the wake
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* source. A follow-up turn will replace ext1 with a true LP-core
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* polling program that can debounce / threshold the accelerometer
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* signal in software, dropping standby current from ~10 µA to ~5 µA.
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*/
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#include "sdkconfig.h"
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#if defined(CONFIG_IDF_TARGET_ESP32C6) && defined(CONFIG_ULP_COPROC_TYPE_LP_CORE)
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#include "c6_lp_core.h"
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#include "esp_log.h"
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#include "esp_sleep.h"
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#include "driver/rtc_io.h"
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#include "soc/soc_caps.h"
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static const char *TAG = "c6_lp";
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static int s_wake_gpio = -1;
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static bool s_active_high = true;
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static bool s_armed = false;
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esp_err_t c6_lp_core_arm(int wake_gpio, bool active_high)
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{
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if (wake_gpio < 0) {
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ESP_LOGE(TAG, "invalid wake_gpio=%d", wake_gpio);
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return ESP_ERR_INVALID_ARG;
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}
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s_wake_gpio = wake_gpio;
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s_active_high = active_high;
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/* GPIO must be in the LP/RTC domain for deep-sleep wake. */
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esp_err_t ret = rtc_gpio_init(wake_gpio);
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if (ret != ESP_OK) {
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ESP_LOGE(TAG, "rtc_gpio_init(%d) failed: %s", wake_gpio, esp_err_to_name(ret));
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return ret;
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}
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rtc_gpio_set_direction(wake_gpio, RTC_GPIO_MODE_INPUT_ONLY);
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/* On the C6, deep-sleep GPIO wake is esp_deep_sleep_enable_gpio_wakeup. */
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uint64_t mask = 1ULL << wake_gpio;
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esp_deepsleep_gpio_wake_up_mode_t mode = active_high
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? ESP_GPIO_WAKEUP_GPIO_HIGH
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: ESP_GPIO_WAKEUP_GPIO_LOW;
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ret = esp_deep_sleep_enable_gpio_wakeup(mask, mode);
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if (ret != ESP_OK) {
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ESP_LOGE(TAG, "enable_gpio_wakeup failed: %s", esp_err_to_name(ret));
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return ret;
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}
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s_armed = true;
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ESP_LOGI(TAG, "armed: wake_gpio=%d active_%s",
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wake_gpio, active_high ? "high" : "low");
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return ESP_OK;
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}
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void c6_lp_core_hibernate_and_wait(void)
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{
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if (!s_armed) {
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ESP_LOGW(TAG, "hibernate called without arm — sleeping with no wake source");
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}
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/* Configure for hibernation: power down everything except what's needed
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* to retain the wake source. On C6 the RTC peripheral domain is the
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* only one we need to gate explicitly — RTC_SLOW_MEM / RTC_FAST_MEM
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* aren't separate power domains on the C6 SoC. */
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esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_OFF);
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ESP_LOGI(TAG, "entering deep sleep — target ≤5 µA");
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esp_deep_sleep_start();
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/* Never returns. */
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}
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bool c6_lp_core_was_motion_wake(void)
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{
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esp_sleep_wakeup_cause_t cause = esp_sleep_get_wakeup_cause();
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return cause == ESP_SLEEP_WAKEUP_GPIO || cause == ESP_SLEEP_WAKEUP_EXT1;
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}
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#endif /* CONFIG_IDF_TARGET_ESP32C6 && CONFIG_ULP_COPROC_TYPE_LP_CORE */
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