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https://github.com/ruvnet/RuView
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ruv
66523843e6
After 3 systematic hypotheses tested + rejected (radio coex, OpenThread shadowing, manual RX re-arm), the 802.15.4 leader-election bug is narrowed to: TX path works perfectly (~10/s clean, 0 fail), but the RX path stops after exactly 1 frame. Manual esp_ieee802154_receive() from either callback bootloops the driver (verified across all 3 boards). The IDF reference example uses the same handle_done-only pattern as this code, implying the driver should auto-restart RX — but empirically doesn't here. Either a half-duplex radio state issue or an IDF v5.4 bug. Tracked as known issue D1 in WITNESS-LOG-110. Changes shipped: - c6_twt.c: ESP_ERR_INVALID_ARG added to graceful-fallback list (empirically: ruv.net AP advertises TWT Responder=0, IDF driver validates against AP HE capability and rejects with INVALID_ARG) - c6_timesync.c: diagnostic counters (s_tx_count, s_tx_fail, s_rx_count, s_rx_magic_match) + per-10-beacon log line preserved so future investigation has the diagnostic harness ready - sdkconfig.defaults.esp32c6: 15.4 channel default 15 → 26 (non-overlap with WiFi 2.4 GHz channels), OpenThread disabled (we use raw 15.4) - promiscuous=true on the radio (broadcast frames addressed to 0xFFFF) - WITNESS-LOG-110 §D1 expanded with the full diagnostic trace + 3-hypothesis investigation record Cross-node sync claim (B3) BLOCKED until either an IDF maintainer trace or a working multi-board reference is available. The other three SOTA dimensions (HE-LTF, TWT cadence, 5 µA hibernation) are also still unverified and need different hardware (11ax AP, INA meter) — honestly recorded in §B. Tracking: ruvnet/RuView#762, task #30 closed as known-issue. Co-Authored-By: claude-flow <ruv@ruv.net>
76 lines
2.9 KiB
Plaintext
76 lines
2.9 KiB
Plaintext
# ESP32-C6 CSI Node — Target overlay (ADR-110)
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#
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# Auto-applied by ESP-IDF when CONFIG_IDF_TARGET=esp32c6.
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# Layered on top of sdkconfig.defaults — only the differences live here.
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#
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# Build:
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# idf.py set-target esp32c6
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# idf.py build
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#
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# Hardware: stock ESP32-C6 dev board with 4 MB or 8 MB embedded flash.
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# Confirmed on COM6: ESP32-C6 (QFN40) rev v0.2, 8 MB flash, 320 KiB SRAM.
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# ── Target ──
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CONFIG_IDF_TARGET="esp32c6"
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# ── Flash & partitions (4 MB — common across C6 dev boards) ──
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CONFIG_PARTITION_TABLE_CUSTOM=y
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CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions_4mb.csv"
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CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y
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CONFIG_ESPTOOLPY_FLASHSIZE="4MB"
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# ── CSI (required) ──
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CONFIG_ESP_WIFI_CSI_ENABLED=y
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# ── ADR-110 P2 & P3: Wi-Fi 6 / iTWT ──
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# IDF v5.4 exposes neither ESP_WIFI_11AX_SUPPORT nor ESP_WIFI_ITWT_SUPPORT as
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# user Kconfig — they're SoC capabilities (SOC_WIFI_HE_SUPPORT) auto-enabled
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# on chips that have HE support (C6/C5). WPA3 is opt-in:
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CONFIG_ESP_WIFI_ENABLE_WPA3_SAE=y
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# ── ADR-110 P4: 802.15.4 (raw, no OpenThread) ──
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# IEEE 802.15.4 PHY enabled for our raw beacon protocol in c6_timesync.c.
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# OpenThread is DISABLED — empirically (ch15 + ch26 tested with the same
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# negative result), enabling OpenThread MTD caused our weak-symbol overrides
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# of esp_ieee802154_receive_done/transmit_done to never fire, breaking
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# leader election. Raw 802.15.4 mode is what we actually need: a private
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# mesh protocol on a private channel, no Thread network attach.
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CONFIG_IEEE802154_ENABLED=y
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CONFIG_OPENTHREAD_ENABLED=n
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# ADR-110 P4: 802.15.4 channel override.
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# Default Kconfig value is 15 (2425 MHz). On the 2.4 GHz radio that's
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# directly under WiFi channel 5 (2432 MHz). Channel 26 = 2480 MHz is on
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# the WiFi guard band above channel 14, giving the 15.4 path room to RX
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# without competing with WiFi traffic for radio time.
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CONFIG_C6_TIMESYNC_CHANNEL=26
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# ── ADR-110 P5: LP-core (deep-sleep coprocessor) ──
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# Enable the LP RISC-V core so c6_lp_core.c can ship a wake-on-motion stub.
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CONFIG_ULP_COPROC_ENABLED=y
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CONFIG_ULP_COPROC_TYPE_LP_CORE=y
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CONFIG_ULP_COPROC_RESERVE_MEM=8192
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# ── No display, no WASM, no mmWave on the C6 research target ──
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# Display (ADR-045) needs 8 MB + native USB-OTG framebuffer hooks.
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# WASM3 (ADR-040) needs PSRAM for hot-loadable modules.
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# mmWave (Seeed MR60BHA2 on COM4) is a separate board.
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# CONFIG_DISPLAY_ENABLE is not set
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# CONFIG_WASM_ENABLE is not set
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# ── Compiler ──
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CONFIG_COMPILER_OPTIMIZATION_SIZE=y
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# ── Logging ──
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CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y
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CONFIG_LOG_DEFAULT_LEVEL_INFO=y
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# ── lwIP / FreeRTOS — same as S3 path ──
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CONFIG_LWIP_SO_RCVBUF=y
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CONFIG_ESP_MAIN_TASK_STACK_SIZE=8192
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CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=8192
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# ── Power: keep CPU at max 160 MHz (C6 ceiling) for DSP throughput ──
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CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_160=y
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CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=160
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