Add SystemVerilog support

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Sean McLoughlin

2021-03-10 21:35:14 -08:00

committed by David Peter

parent db57454f3f

commit d89fa3ebc2

8 changed files with 215 additions and 0 deletions

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assets/syntaxes/02_Extra/SystemVerilog

Vendored Submodule

+1

Submodule assets/syntaxes/02_Extra/SystemVerilog added at 7eca705e87