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Add SystemVerilog support

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This commit is contained in:
Sean McLoughlin
2021-03-10 21:35:14 -08:00
committed by David Peter
parent db57454f3f
commit d89fa3ebc2
8 changed files with 215 additions and 0 deletions
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src/assets.rs
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@@ -450,6 +450,7 @@ mod tests {
assert_eq!(test.syntax_for_file("test.sass"), "Sass");
assert_eq!(test.syntax_for_file("test.js"), "JavaScript (Babel)");
assert_eq!(test.syntax_for_file("test.fs"), "F#");
assert_eq!(test.syntax_for_file("test.v"), "Verilog");
}
#[test]