build(deps): bump assets/syntaxes/02_Extra/SystemVerilog

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Bumps [assets/syntaxes/02_Extra/SystemVerilog](https://github.com/TheClams/SystemVerilog) from `7eca705` to `b340f1c`.
- [Commits](https://github.com/TheClams/SystemVerilog/compare/7eca705e87f87b94478fe222fc91d54d488cc8e3...b340f1c7f6a38d4da9f77be5abd6d455e5da7641)

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updated-dependencies:
- dependency-name: assets/syntaxes/02_Extra/SystemVerilog
  dependency-version: b340f1c7f6a38d4da9f77be5abd6d455e5da7641
  dependency-type: direct:production
...

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dependabot[bot]

2025-11-01 09:27:44 +00:00

committed by GitHub

parent 490e1580ad

commit 528aa4fedd

1 changed files with 1 additions and 1 deletions

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assets/syntaxes/02_Extra/SystemVerilog

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+1 -1

Submodule assets/syntaxes/02_Extra/SystemVerilog updated: 7eca705e87...b340f1c7f6